Solving the Dynamic Stability Challenge of Automatic Gain-Controlled Phase-Locked Loops: A Robust Alternative via Enhanced SRF-PLL Design and Implementation

This study presents a robust alternative to conventional phase-locked loop (PLL) architectures through the design and real-time implementation of an enhanced Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) for single-phase inverter systems. Targeting the inherent dynamic stability limitations of Automatic Gain-Controlled PLLs (AGC-PLLs), the proposed SRF-PLL demonstrates superior performance in transient response and tracking accuracy. Comparative evaluations under diverse dynamic operating conditions—including phase angle jumps, voltage sags/swells, frequency steps, noise, and harmonic distortion—highlight its resilience and adaptability. Experimental results reveal a substantial improvement in dynamic response, achieving 2.5 to 6 times faster settling times depending on the operating condition. Moreover, peak-to-peak oscillations were significantly suppressed, with deviations reduced from 2° to nearly 0° under a 5 Hz frequency step scenario, even in the presence of 3rd order harmonic injection. For a 40° phase angle step, the proposed system achieves a fivefold improvement in attenuation time (0.03 s vs. 0.11 s) compared to the AGC-PLL. Under voltage sag conditions with noise and 3rd order harmonic injection, the enhanced SRF-PLL reduces the attenuation time from 0.2 s to 0.08 s. During voltage swell scenarios, it further improves the response time from 0.025 s to 0.01 s. These findings confirm the practical benefits and efficiency of the enhanced SRF-PLL for applications requiring precise and reliable phase tracking and synchronization.