<?xml version="1.0" encoding="UTF-8"?><OAI-PMH xmlns="http://www.openarchives.org/OAI/2.0/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/ http://www.openarchives.org/OAI/2.0/OAI-PMH.xsd"><responseDate>2026-10-23T17:55:19Z</responseDate><request verb="GetRecord" identifier="oai:gumushane-rdlopen.rawdatalibrary.net:gumushane/14149" metadataPrefix="oai_dc">https://gumushane-rdlopen.rawdatalibrary.net/oai/request</request><GetRecord><record><header><identifier>oai:gumushane-rdlopen.rawdatalibrary.net:gumushane/14149</identifier><datestamp>2026-10-22T11:36:48Z</datestamp><setSpec>openaire</setSpec><setSpec>driver</setSpec><setSpec>com_gumushane_10000</setSpec><setSpec>col_gumushane_10001</setSpec><setSpec>com_gumushane_10007</setSpec><setSpec>col_gumushane_10171</setSpec><setSpec>com_gumushane_10010</setSpec><setSpec>col_gumushane_10175</setSpec></header><metadata><oai_dc:dc xmlns:oai_dc="http://www.openarchives.org/OAI/2.0/oai_dc/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.openarchives.org/OAI/2.0/oai_dc/ http://www.openarchives.org/OAI/2.0/oai_dc.xsd"><dc:title>Solving the Dynamic Stability Challenge of Automatic Gain-Controlled Phase-Locked Loops: A Robust Alternative via Enhanced SRF-PLL Design and Implementation</dc:title><dc:creator>Yanarateş, Cağfer</dc:creator><dc:creator>Altan, Aytaç</dc:creator><dc:subject>Automatic gain control</dc:subject><dc:subject>diverse dynamic operating conditions</dc:subject><dc:subject>phase-locked loops</dc:subject><dc:subject>prefiltering resonant controller</dc:subject><dc:subject>synchronous reference frame</dc:subject><dc:subject>time and frequency domain analysis</dc:subject><dc:description>This study presents a robust alternative to conventional phase-locked loop (PLL) architectures through the design and real-time implementation of an enhanced Synchronous Reference Frame Phase-Locked Loop (SRF-PLL) for single-phase inverter systems. Targeting the inherent dynamic stability limitations of Automatic Gain-Controlled PLLs (AGC-PLLs), the proposed SRF-PLL demonstrates superior performance in transient response and tracking accuracy. Comparative evaluations under diverse dynamic operating conditions—including phase angle jumps, voltage sags/swells, frequency steps, noise, and harmonic distortion—highlight its resilience and adaptability. Experimental results reveal a substantial improvement in dynamic response, achieving 2.5 to 6 times faster settling times depending on the operating condition. Moreover, peak-to-peak oscillations were significantly suppressed, with deviations reduced from 2° to nearly 0° under a 5 Hz frequency step scenario, even in the presence of 3rd order harmonic injection. For a 40° phase angle step, the proposed system achieves a fivefold improvement in attenuation time (0.03 s vs. 0.11 s) compared to the AGC-PLL. Under voltage sag conditions with noise and 3rd order harmonic injection, the enhanced SRF-PLL reduces the attenuation time from 0.2 s to 0.08 s. During voltage swell scenarios, it further improves the response time from 0.025 s to 0.01 s. These findings confirm the practical benefits and efficiency of the enhanced SRF-PLL for applications requiring precise and reliable phase tracking and synchronization.</dc:description><dc:publisher>Institute of Electrical and Electronics Engineers Inc.</dc:publisher><dc:date>2025</dc:date><dc:type>Article</dc:type><dc:identifier>https://rdlopen.rawdatalibrary.net/r/gumushane/14149</dc:identifier><dc:identifier>https://doi.org/10.1109/access.2025.3591724</dc:identifier><dc:identifier>2169-3536</dc:identifier><dc:language>en</dc:language><dc:relation>IEEE Access</dc:relation><dc:rights>info:eu-repo/semantics/openAccess</dc:rights><dc:type>info:eu-repo/semantics/article</dc:type><dc:identifier>https://gumushane-rdlopen.rawdatalibrary.net/tr/items/gumushane/14149</dc:identifier></oai_dc:dc></metadata></record></GetRecord></OAI-PMH>